{ "all_lec_ok": true, "all_naive_refuted": true, "all_postsynth_proven": true, "engines": [ "Pono `-e ind` \u2014 temporal k-induction on the gate-level netlist (BTOR2)", "Pono `-e mbic3` \u2014 IC3/PDR on the gate-level netlist (BTOR2); HWMCC'25 word-level winner", "eqy + SymbiYosys (bitwuzla) \u2014 logic-equivalence RTL == gate netlist", "Pono `-e bmc` \u2014 bounded refutation of the guard-removed naive twin" ], "executed": true, "explicit_non_claim": "Formal property proof on a technology-mapped GATE-LEVEL netlist (re-proven after synthesis by two independent HWMCC-winning engines, Pono k-induction AND Pono IC3/PDR), plus a logic-equivalence certificate (eqy) that RTL == netlist, plus open-PDK synthesis/P&R/STA ESTIMATES on the SkyWater SKY130 OPEN PDK. NOT fabricated silicon, NOT a tapeout, NOT measured power, NOT signed-off timing on a commercial node, NOT over-the-air. The netlist refines the SAME abstract guard the z3/BFS/Lean model already certifies; engines certify ordering/safety, never a dB or byte. Abstraction-gap risk MEDIUM -> LOW, not to zero.", "min_engines_safe": 2, "modules": { "anti_clogging_gate": { "backs_wall": "19.7M x PQC KEM-context reconnect-flood wall", "gate_cells": 6, "logic_equivalence_check": { "n_state_partitions_proved": 6, "non_vacuous": true, "rtl_equiv_netlist": true, "tool": "eqy + SymbiYosys (bitwuzla)" }, "naive_module": "anti_clogging_gate_naive", "naive_refuted_on_netlist": true, "physical_sky130": { "area_um2": 185.1776, "cell_count_sky130": 17.0, "fmax_mhz": 434.4992396263307, "gds_bytes": null, "gdsii_present": false, "lec_rtl_eq_sky130_netlist": false, "lib": "sky130_fd_sc_hd__tt_025C_1v80 (typical, 25C, 1.80V)", "longest_path_ns": 2.3015, "note": "real SKY130 standard-cell mapping (yosys dfflibmap+abc -liberty) + OpenSTA timing \u2014 open-tool ESTIMATES on the open PDK; full P&R/GDSII is a stretch (skip-clean if absent).", "pdk": "SkyWater SKY130 (sky130_fd_sc_hd, open PDK, Apache-2.0)", "ran": true, "sky130_netlist_present": true, "worst_slack_ns": null }, "postsynth_proof": { "engine_refs": "Pono (Stanford, BSD-3): k-induction + IC3/PDR (HWMCC'25 word-level winner)", "engines": { "pono_ic3_pdr": true, "pono_kinduction": true }, "level": "technology-mapped gate-level netlist (synth -> techmap -> abc gate map)", "n_engines_agree_safe": 2, "proven_unbounded_on_netlist": true }, "property": "(!insec && !oo) == no_state_before_validation AND ordered_acquisition", "verilog": "rtl/anti_clogging_gate.v", "verilog_sha256": "8b46e34489bfd2560aae1680b7ce9a8e17dee6d0bb5cdb0d51745684eae08459" }, "bounded_reorder_credit": { "backs_wall": "67.1M x UEC reorder-memory wall", "gate_cells": 5, "logic_equivalence_check": { "n_state_partitions_proved": 1, "non_vacuous": true, "rtl_equiv_netlist": true, "tool": "eqy + SymbiYosys (bitwuzla)" }, "naive_module": "bounded_reorder_credit_naive", "naive_refuted_on_netlist": true, "physical_sky130": { "area_um2": 270.2592, "cell_count_sky130": 29.0, "fmax_mhz": 2691.0656620021527, "gds_bytes": null, "gdsii_present": false, "lec_rtl_eq_sky130_netlist": false, "lib": "sky130_fd_sc_hd__tt_025C_1v80 (typical, 25C, 1.80V)", "longest_path_ns": 0.3716, "note": "real SKY130 standard-cell mapping (yosys dfflibmap+abc -liberty) + OpenSTA timing \u2014 open-tool ESTIMATES on the open PDK; full P&R/GDSII is a stretch (skip-clean if absent).", "pdk": "SkyWater SKY130 (sky130_fd_sc_hd, open PDK, Apache-2.0)", "ran": true, "sky130_netlist_present": true, "worst_slack_ns": null }, "postsynth_proof": { "engine_refs": "Pono (Stanford, BSD-3): k-induction + IC3/PDR (HWMCC'25 word-level winner)", "engines": { "pono_ic3_pdr": true, "pono_kinduction": true }, "level": "technology-mapped gate-level netlist (synth -> techmap -> abc gate map)", "n_engines_agree_safe": 2, "proven_unbounded_on_netlist": true }, "property": "outstanding <= K (bounded reorder buffer never overflows)", "verilog": "rtl/bounded_reorder_credit.v", "verilog_sha256": "43b2a9bc9942d13f091817ed620698721633e320e0fa919b05faa7f7f6444f91" }, "ordered_acquire": { "backs_wall": "CXL/UEC forward-progress (no fabric deadlock)", "gate_cells": 1, "logic_equivalence_check": { "n_state_partitions_proved": 2, "non_vacuous": true, "rtl_equiv_netlist": true, "tool": "eqy + SymbiYosys (bitwuzla)" }, "naive_module": "ordered_acquire_naive", "naive_refuted_on_netlist": true, "physical_sky130": { "area_um2": 70.0672, "cell_count_sky130": 8.0, "fmax_mhz": 3186.7431485022303, "gds_bytes": null, "gdsii_present": false, "lec_rtl_eq_sky130_netlist": false, "lib": "sky130_fd_sc_hd__tt_025C_1v80 (typical, 25C, 1.80V)", "longest_path_ns": 0.3138, "note": "real SKY130 standard-cell mapping (yosys dfflibmap+abc -liberty) + OpenSTA timing \u2014 open-tool ESTIMATES on the open PDK; full P&R/GDSII is a stretch (skip-clean if absent).", "pdk": "SkyWater SKY130 (sky130_fd_sc_hd, open PDK, Apache-2.0)", "ran": true, "sky130_netlist_present": true, "worst_slack_ns": null }, "postsynth_proof": { "engine_refs": "Pono (Stanford, BSD-3): k-induction + IC3/PDR (HWMCC'25 word-level winner)", "engines": { "pono_ic3_pdr": true, "pono_kinduction": true }, "level": "technology-mapped gate-level netlist (synth -> techmap -> abc gate map)", "n_engines_agree_safe": 2, "proven_unbounded_on_netlist": true }, "property": "held_hi -> held_lo (ordered acquisition; forecloses 2-resource circular wait)", "verilog": "rtl/ordered_acquire.v", "verilog_sha256": "7b65a36f5c47b1a29a3d3be947f7aeecbd0019dcd0068bb0649191847af83cdd" } }, "n_modules": 3, "physical_flow": { "note": "OpenLane SKY130 synthesis/P&R/STA/GDSII \u2014 folded in per-module from artifacts/backends/asic_openlane/ when present; otherwise skip-clean (the formal gate-level proof + LEC above stand independently).", "pdk": "SkyWater SKY130 (open PDK, Apache-2.0) via OpenLane", "ran_here": true }, "proof_hash": "c08d7f081300870c1e5d1fb6512afd12587ea7dd423688c276910ea4b51b76dc", "refinement_note": "the v30 RTL rung lowered one step: the SAME safety invariant, re-proven AFTER technology mapping (gate-level), cross-checked by two independent competition-grade engines and a logic-equivalence certificate; rtl -> netlist -> high -> mid -> abstract -> spec", "schema": "v38-asic-flow", "skipped": false, "title": "To the Gates (open-PDK; NOT fabricated silicon): the load-bearing guards re-proven on the technology-mapped gate-level netlist by two HWMCC-winning engines, RTL==netlist by LEC, and pushed through the SKY130 open-PDK synthesis/P&R/STA flow", "two_engine_ok": true }