{
 "_doc": "The lab's current claim and limits for one result, copied word for word from the portfolio's current-claims file at the line named here. A value this site does not print in full is replaced by its sha256 and byte count, with the reason; the excerpts beside it are copied word for word from the same value. Nothing here is written by hand.",
 "result": "wireless-pqc:netlist-equivalence-422",
 "title": "Formal netlist equivalence for the admission engine, through technology mapping: the published sky130 netlist proved equivalent to the RTL, 274 of 274 $equiv cells",
 "claim": "Formal netlist equivalence for the admission engine through technology mapping: the sky130_fd_sc_hd netlist whose area and delay are published is proved equivalent to the RTL, 274 of 274 $equiv cells, over SkyWater's own functional cell models; the synth step alone is also proved, 422 of 422 $equiv cells over yosys simcell models.",
 "limits": "4816.17 ps ≈ 207.6 MHz must never travel without WireLoad = \"none\". No place-and-route, no parasitics, no OpenSTA, no sign-off corner, no tape-out. The second area figure in the same block — 8744.64 — is abc's internal unit, not µm²; the µm² figure is 14850.4928 and belongs to this module alone. Both proofs are yosys equiv_make + equiv_induct with state elements matched by name: from any state in which the matched flip-flops agree, the designs agree on every input sequence -- two-valued (no X), not a reset-reachability proof, no timing. The 274 (gates.formal_netlist_equivalence.mapped_netlist, since 2026-09-24) is the netlist file whose cells, area and delay are published, read against SkyWater's functional Verilog models of the 67 sized cells it uses, vendored unmodified with per-file sha256 in hw/pqc_admit/lib/sky130_fd_sc_hd_models/MANIFEST.json (google/skywater-pdk-libs-sky130_fd_sc_hd at ac7fb61f06e6); yosys cannot parse the two UDP tables the flip-flop models use, so two stand-ins written in this repository are used and are checked against those tables in iverilog over every two-valued case. The 422 is the synth step alone, against yosys simcell models, and no plant has yet moved it. The yosys version is now recorded in the artifact. Superseded wording, kept in this entry's claim_history: the sky130 mapping was \"a separate gate\" that no proof covered.",
 "claim_excerpts": [],
 "limits_excerpts": [],
 "lab_commit": "c5f34eda4cc9f7f86308a5db1cfa75efcd4c6841",
 "source": {
  "file": "portfolio-control registry/CLAIMS_CURRENT.jsonl",
  "line": 55,
  "sha256": "81776df15a1498abec7228ea179c952d01c54e031ffd4144498a30660963074b"
 },
 "evidence": "/receipts/wireless-pqc/results/netlist-equivalence-422.json",
 "copied_utc": "2026-10-03T16:11:27Z"
}